Pentium
®
III Processor for the SC242 at 450 MHz to 733 MHz
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Second Level (L2) Cache Implementation ........................................................... 9
AGTL+ Bus Topology ..........................................................................................14
Stop Clock State Machine ...................................................................................14
BSEL[1:0] Example for a 100 MHz System Design
(100 MHz Processor Installed) ............................................................................22
BSEL[1:0] Example for a 100/133 MHz Capable System
(100 MHz Processor Installed) ............................................................................23
BSEL[1:0] Example for a 100/133 MHz Capable System
(133 MHz Processor Installed) ............................................................................23
BCLK, PICCLK, and TCK Generic Clock Waveform...........................................36
System Bus Valid Delay Timings ........................................................................36
System Bus Setup and Hold Timings..................................................................37
System Bus Reset and Configuration Timings....................................................37
Power-On Reset and Configuration Timings.......................................................37
Test Timings (TAP Connection) ..........................................................................38
Test Reset Timings .............................................................................................38
BCLK and PICCLK Generic Clock Waveform .....................................................39
Maximum Acceptable AGTL+ and Non-AGTL+ Overshoot/Undershoot
Waveform ............................................................................................................45
Low to High AGTL+ and Non-AGTL+ Receiver Ringback Tolerance .................47
Signal Overshoot/Undershoot, Settling Limit, and Ringback ..............................47
S.E.C.Cartridge — 3-Dimensional View..............................................................48
S.E.C.Cartridge 2 — Substrate View ..................................................................49
Processor Functional Die Layout (CPUID 068xh) ...............................................50
S.E.C.C. Packaged Processor — Multiple Views................................................52
S.E.C.C. Packaged Processor — Extended Thermal Plate Side Dimensions ....53
S.E.C.C. Packaged Processor — Bottom View Dimensions...............................53
S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate Lug,
and Cover Lug Dimensions .................................................................................54
S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate,
and Cover Detail Dimensions (Reference Dimensions Only)..............................55
S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment
Detail Dimensions ...............................................................................................56
S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment
Detail Dimensions, Continued .............................................................................57
S.E.C.C. Packaged Processor Substrate — Edge Finger Contact Dimensions .57
S.E.C.C. Packaged Processor Substrate — Edge Finger Contact
Dimensions, Detail A ...........................................................................................58
Intel
®
Pentium® III Processor Markings (S.E.C.C. Packaged Processor)...........58
S.E.C.C.2 Packaged Processor — Multiple Views..............................................59
S.E.C.C.2 Packaged Processor Assembly — Primary View...............................60
S.E.C.C.2 Packaged Processor Assembly — Cover View with Dimensions ......60
S.E.C.C.2 Packaged Processor Assembly — Heat Sink Attach Boss Section ...61
S.E.C.C.2 Packaged Processor Assembly — Side View ....................................61
Detail View of Cover in the Vicinity of the Substrate Attach Features.................61
S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact
Dimensions..........................................................................................................62
S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact
Dimensions (Detail A)..........................................................................................62
Datasheet
5
INTEL [ INTEL CORPORATION ]
