80186/80188
Intel recommends the following values for crystal se-
lection parameters:
FUNCTIONAL DESCRIPTION
Introduction
Temperature Range:
ESR (Equivalent Series Resistance):
0 to 70 C
§
30X max
7.0 pf max
C
C
(Shunt Capacitance of Crystal):
(Load Capacitance):
0
The following Functional Description describes the
base architecture of the 80186. The 80186 is a very
high integration 16-bit microprocessor. It combines
15–20 of the most common microprocessor system
components onto one chip while providing twice the
performance of the standard 8086. The 80186 is ob-
ject code compatible with the 8086/8088 microproc-
essors and adds 10 new instruction types to the
8086/8088 instruction set.
g
20 pf 2 pf
1 mW max
1
Drive Level:
Clock Generator
The clock generator provides the 50% duty cycle
processor clock for the processor. It does this by
dividing the oscillator output by 2 forming the sym-
metrical clock. If an external oscillator is used, the
state of the clock generator will change on the fall-
ing edge of the oscillator signal. The CLKOUT pin
provides the processor clock signal for use outside
the device. This may be used to drive other system
components. All timings are referenced to the output
clock.
For more detailed information on the architecture,
please refer to the 80C186XL/80C188XL User’s
Manual. The 80186 and the 80186XL devices are
functionally and register compatible.
CLOCK GENERATOR
The processor provides an on-chip clock generator
for both internal and external clock generation. The
clock generator features a crystal oscillator, a divide-
by-two counter, synchronous and asynchronous
ready inputs, and reset circuitry.
READY Synchronization
The processor provides both synchronous and asyn-
chronous ready inputs. In addition, the processor, as
part of the integrated chip-select logic, has the capa-
bility to program WAIT states for memory and
peripheral blocks.
Oscillator
The oscillator circuit is designed to be used with a
parallel resonant fundamental mode crystal. This is
used as the time base for the processor. The crystal
frequency selected will be double the CPU clock fre-
quency. Use of an LC or RC circuit is not recom-
mended with this oscillator. If an external oscillator is
used, it can be connected directly to the input pin X1
in lieu of a crystal. The output of the oscillator is not
directly available outside the processor. The recom-
mended crystal configuration is shown in Figure 5.
RESET Logic
The processor provides both a RES input pin and a
synchronized RESET output pin for use with other
system components. The RES input pin is provided
with hysteresis in order to facilitate power-on Reset
generation via an RC network. RESET output is
guaranteed to remain active for at least five clocks
given a RES input of at least six clocks.
LOCAL BUS CONTROLLER
The processor provides a local bus controller to
generate the local bus control signals. In addition, it
employs a HOLD/HLDA protocol for relinquishing
the local bus to other bus masters. It also provides
outputs that can be used to enable external buffers
and to direct the flow of data on and off the local
bus.
272430–5
x
80186-10 (10 MHz) 20
80186
(8 MHz) 16
Figure 5. Recommended
Crystal Configuration
9
9
INTEL [ INTEL ]
