80186/80188
Table 1. Pin Descriptions (Continued)
Pin
Symbol
Type
Name and Function
No.
A19/S6
A18/S5
A17/S4
A16/S3
65
66
67
68
O
O
O
O
Address Bus Outputs (16–19) and Bus Cycle Status (3–6) indicate the four most
significant address bits during T . These signals are active HIGH. During T , T , T ,
W
and T , the S6 pin is LOW to indicate a CPU-initiated bus cycle or HIGH to indicate a
4
DMA-initiated bus cycle. During the same T-states, S3, S4, and S5 are always LOW.
The status pins float during bus HOLD or RESET.
1
2
3
AD15 (A15)
AD14 (A14)
AD13 (A13)
AD12 (A12)
1
3
5
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Address/Data Bus signals constitute the time multiplexed memory or I/O address (T )
1
and data (T , T , T , and T ) bus. The bus is active HIGH. A is analogous to BHE for
2
3
W
4
0
the lower byte of the data bus, pins D through D . It is LOW during T when a byte is
1
7
0
to be transferred onto the lower portion of the bus in memory or I/O operations. BHE
does not exist on the 80188, as the data bus is only 8 bits wide.
AD11 (A11) 10
AD10 (A10) 12
AD9 (A9)
AD8 (A8)
AD7
14
16
2
AD6
4
AD5
6
AD4
8
AD3
11
13
15
17
AD2
AD1
AD0
BHE/S7
(S7)
64
O
During T the Bus High Enable signal should be used to determine if data is to be
1
enabled onto the most significant half of the data bus; pins D –D . BHE is LOW
15
8
during T for read, write, and interrupt acknowledge cycles when a byte is to be
1
transferred on the higher half of the bus. The S status information is available during
7
T , T , and T . S is logically equivalent to BHE. BHE/S7 floats during HOLD. On the
2
3
4
80188, S7 is high during normal operation.
7
BHE and A0 Encodings (80186 Only)
Function
BHE
A0
Value Value
0
0
1
1
0
1
0
1
Word Transfer
Byte Transfer on upper half of data bus (D15–D8)
Byte Transfer on lower half of data bus (D –D )
7
0
Reserved
ALE/QS0
WR/QS1
61
63
O
O
Address Latch Enable/Queue Status 0 is provided by the processor to latch the
address. ALE is active HIGH. Addresses are guaranteed to be valid on the trailing
edge of ALE. The ALE rising edge is generated off the rising edge of the CLKOUT
immediately preceding T of the associated bus cycle, effectively one-half clock cycle
1
earlier than in the 8086. The trailing edge is generated off the CLKOUT rising edge in
T
as in the 8086. Note that ALE is never floated.
1
Write Strobe/Queue Status 1 indicates that the data on the bus is to be written into a
memory or an I/O device. WR is active for T , T , and T of any write cycle. It is active
2
3
W
LOW, and floats during HOLD. When the processor is in queue status mode, the ALE/
QS0 and WR/QS1 pins provide information about processor/instruction queue
interaction.
QS1
QS0
Queue Operation
0
0
1
1
0
1
1
0
No queue operation
First opcode byte fetched from the queue
Subsequent byte fetched from the queue
Empty the queue
NOTE:
Pin names in parentheses apply to the 80188.
6
6
INTEL [ INTEL ]
