80186/80188
INSTRUCTION SET SUMMARY (Continued)
80186
Clock
Cycles
80188
Clock
Cycles
Function
Format
Comments
PROCESSOR CONTROL
e
e
e
e
e
CLC
CMC
STC
CLD
STD
Clear carry
1 1 1 1 1 0 0 0
1 1 1 1 0 1 0 1
1 1 1 1 1 0 0 1
1 1 1 1 1 1 0 0
1 1 1 1 1 1 0 1
1 1 1 1 1 0 1 0
1 1 1 1 1 0 1 1
1 1 1 1 0 1 0 0
1 0 0 1 1 0 1 1
1 1 1 1 0 0 0 0
1 1 0 1 1 T T T
2
2
2
2
2
2
2
2
6
2
6
2
2
2
2
2
2
2
2
6
3
6
Complement carry
Set carry
Clear direction
Set direction
e
CLI
STI
Clear interrupt
Set interrupt
e
e
HLT
Halt
e
e
0
WAIT
LOCK
Wait
if TEST
e
Bus lock prefix
e
ESC
Processor Extension Escape
mod LLL r/m
(TTT LLL are opcode to processor extension)
1 0 0 1 0 0 0 0
e
NOP
No Operation
3
3
Shaded areas indicate instructions not available in 8086, 8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer.
reg is assigned according to the following:
FOOTNOTES
Segment
The Effective Address (EA) of the memory operand
is computed according to the mod and r/m fields:
reg
Register
00
01
10
11
ES
CS
SS
DS
e
e
e
if mod
if mod
if mod
11 then r/m is treated as REG field
e
00 then DISP
01 then DISP
0*, disp-low and disp-high are absent
disp-low sign-extended to 16-bits, disp-high
e
is absent
e
e
e
disp-high: disp-low
if mod
if r/m
if r/m
if r/m
if r/m
if r/m
if r/m
if r/m
if r/m
10 then DISP
e
e
a
a
a
a
a
a
a
a
a
a
000 then EA
001 then EA
010 then EA
011 then EA
100 then EA
101 then EA
110 then EA
111 then EA
(BX)
(BX)
(BP)
(BP)
(SI)
(DI)
(BP)
(BX)
(SI)
(DI)
(SI)
(DI)
DISP
DISP
DISP
DISP
DISP
DISP
e
e
e
e
e
e
e
e
e
e
e
e
e
REG is assigned according to the following table:
e
e
0)
16-Bit (w
1)
8-Bit (w
a
a
DISP*
DISP
000 AX
001 CX
010 DX
011 BX
100 SP
101 BP
110 SI
000 AL
001 CL
010 DL
011 BL
100 AH
101 CH
110 DH
111 BH
DISP follows 2nd byte of instruction (before data if
required)
e
e
e
110 then EA
*except if mod
disp-high: disp-low.
00 and r/m
111 DI
EA calculation time is 4 clock cycles for all modes,
and is included in the execution times given whenev-
er appropriate.
The physical addresses of all operands addressed
by the BP register are computed using the SS seg-
ment register. The physical addresses of the desti-
nation operands of the string primitive operations
(those addressed by the DI register) are computed
using the ES segment, which may not be overridden.
Segment Override Prefix
0
0
1
reg
1
1
0
32
32
INTEL [ INTEL ]
