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6702PXH 参数 Datasheet PDF下载

6702PXH图片预览
型号: 6702PXH
PDF下载: 下载PDF文件 查看货源
内容描述: 64位PCI中枢 [64-bit PCI Hub]
分类和应用: PC
文件页数/大小: 214 页 / 2554 K
品牌: INTEL [ INTEL ]
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Signal Description  
2.6  
SMBus Interface  
Table 2-8. SMBus Interface Signals  
Signal  
Type  
Description  
SCLK  
SDTA  
I
SMBus Clock  
I/OD SMBus Data  
SMBus Addressing Straps:  
SMBUS[5]  
I
SMBUS[3:1]  
SMBus Addressing:  
Bit 7----------------------------‘1’  
Bit 6----------------------------‘1’  
Bit 5----------------------------SMBUS[5]  
Bit 4----------------------------‘0’  
Bit 3----------------------------SMBUS[3]  
Bit 2----------------------------SMBUS[2]  
Bit 1----------------------------SMBUS[1]  
2.7  
Miscellaneous Signals  
Table 2-9. Miscellaneous Signals  
Signal  
PWROK  
Type  
Description  
I
Power Supply OK: When high indicates that the system power supply has  
stabilized. When low, asynchronously resets the Intel® 6702PXH 64-bit PCI Hub.  
Most of the strap pins on the Intel® 6702PXH 64-bit PCI Hub are sampled on the  
rising edge of this signal. Please refer to Section 2.18.2.1 for details on the timing  
relationship between PWROK, the PCI Express* clocks, and all voltages supplied  
to the Intel® 6702PXH 64-bit Hub.  
RSTIN#  
I
Reset In: When asserted, this signal asynchronously resets the Intel® 6702PXH  
64-bit PCI Hub logic and asserts PAPCIRST# active output from each PCI  
interface. This signal is typically connected to the PAPCIRST# output of the ICH5  
or the PLTRST# output of the ICH6.  
TCK  
TDI  
I
I
TAP Clock In: This is the input clock to the JTAG TAP controller active rising  
edge, which runs from 0-16 MHz.  
Test Data In: This is the serial data input to the JTAG BSCAN shift register chain  
and to the BSCAN control logic. This is latched in on the rising edge of TCK. If not  
using JTAG, this signal can be a no connect.  
TDO  
TMS  
O
I
Test Data Output: This is the serial data output from the BSCAN logic. If not  
using JTAG, this signal can be a no connect.  
Test Mode Select: This signal controls the TAP controller state machine to move  
to different states and is sampled on the rising edge of TCK. This signal can be a  
no connect if JTAG is not being used.  
TRST#  
I
Test Reset In: This signal is used to asynchronously reset the JTAG BSCAN  
logic.  
24  
Intel® 6702PXH 64-bit PCI Hub Datasheet