Signal Description
2.3
PCI Bus Interface 64-bit Extension
Table 2-3. PCI Bus Interface 64-bit Extension Interface A Signals
Signal
Type Description
PAACK64#
I/O
I/O
PCI Interface Acknowledge 64-bit Transfer: This signal is asserted by the
target only when PAREQ64# is asserted by the initiator. It indicates the target’s
ability to transfer data using 64 bits. It has the same timing as PADEVSEL#.
PAAD[63:32]
PCI Address/Data: These signals are a multiplexed address and data bus. This
bus provides an additional 32 bits to the PCI bus. During the data phases of a
transaction, the initiator drives the upper 32 bits of 64-bit write data, or the target
drives the upper 32 bits of 64-bit read data, when PAREQ64# and PAACK64# are
both asserted.
PACBE_[7:4]#
I/O
Bus Command and Byte Enables (Upper 4 bits): These signals are a
multiplexed command field and byte enable field. For both read and write
transactions, the initiator will drive byte enables for the PAAD[63:32] data bits on
PACBE_[7:4]# during the data phases when PAREQ64# and PAACK64# are both
asserted.
PAPAR64
I/O
I/O
PCI Interface Upper 32-bits Parity: This signal carries the even parity of the
36 bits of PAAD[63:32] and PACBE_[7:4]# for both address and data phases.
PAREQ64#
PCI interface Request 64-bit Transfer: This signal is asserted by the initiator to
indicate that the initiator is requesting a 64-bit data transfer. It has the same timing
as PAFRAME#. When the Intel® 6702PXH 64-bit PCI Hub is the initiator, this
signal is an output. When the Intel® 6702PXH 64-bit PCI Hub is the target, this
signal is an input.
2.4
Interrupt Interface
This section lists the interrupt interface signals.
Table 2-4. Interrupt Interface A Signals
Signal
PAIRQ_[15:0]#
Type Description
I
Interrupt Request Bus: The PAIRQ# lines from PCI interrupts PIRQ[A:D] can be
routed to these interrupt lines.
18
Intel® 6702PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
