Introduction
1.2.4
1.2.5
I/OxAPIC Controller
The Intel® 6702PXH 64-bit PCI Hub contains one I/OxAPIC controller, which reside on the
primary bus. The intended use of this controller for the Intel® 6702PXH 64-bit PCI Hub is to have
the interrupt from PCI bus A connected to the interrupt controller on device 0, function 1.
SMBus Interface
The SMBus interface can be used for system and power management related tasks. The interface is
compliant with System Management Bus Specification, Revision 2.0. The SMBus interface allows
full read/write access to all configuration and memory spaces in the Intel® 6702PXH 64-bit PCI
Hub.
1.2.6
JTAG
The Intel® 6702PXH 64-bit PCI Hub has a JTAG (TAP) port compliant with the IEEE Standard
Test Access Port and Boundary Scan Architecture 1149.1 Specifications. The TAP controller is
accessed serially through five dedicated pins. This can be used for test and debug purposes. System
board interconnects can be DC tested using the boundary scan logic in pads.
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Intel® 6702PXH 64-bit PCI Hub Datasheet
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INTEL [ INTEL ]
