Clocking
The PLL will also operate with the REFCLK at 100 MHz during special transparent mode
testing. Since there is no high speed link operation, there can be looser requirements
for jitter and no SSC.
8.4
FBD Lane Frame Clocks
Each FBD I/O lane also sources a frame clock at core frequency that is matched to the
parallel data sourced by the lane. These are used during initialization to capture data in
training sequences and to align data across the link.
8.5
Clock Ratios
The core, DDR and FBD link clock domains are fixed in a 1:2:12 ratio. The SMBus
asynchronous subsystem need not scale. The supported clock ratios are shown in
Table 8-2.
Table 8-2.
AMB Clock Ratios
FBD Link Data
DDR Data Rate Core Frequency
Ref Clk
FBD Link : Core
Core : DDR
Rate
3.2 Gb/s
4.0 Gb/s
533 Mb/s
667 Mb/s
266 MHz
333 MHz
133 MHz
167 MHz
12 : 1
12 : 1
1 : 2
1 : 2
8.6
8.7
DDR DRAM Clock Support
The DDR command clocks (CLK[3:0], CLK[3:0])are generated by the AMB. They operate at
1X the core frequency for DDR2.
The write strobes operate at the same frequency as the CLK/CLK signals. Write data
and check bits are aligned to both the rising and falling edges of the write strobe.
The source-synchronous read strobes operate at the same rates as the write strobes.
Each read strobe will be individually aligned with its portion of the data and check-bits.
SMBus
The SMBus clock is synchronized to the core clock. Data is driven into the AMB with
respect to the serial clock signal. Data received on the data signal with respect to the
clock signal will be synchronized to the core using a metastability hardened
synchronizer guaranteeing an MTBF greater than 107 years. When inactive, the serial
clock should be deasserted (High). The serial clock frequency is 100 kHz.
8.8
Clock Pins
Table 8-3.
Clock Pins (Sheet 1 of 2)
Pin Name
Pin Description
SCK
AMB clock
SCK
AMB clock (Complement)
analog power supply for PLL
analog ground for PLL
TAP clock
VCCAPLL
VSSAPLL
TCK
86
Intel® 6400/6402 Advanced Memory Buffer Datasheet
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