DDR Interface
DCALCSR until the start bit is cleared. After the start bit is cleared, firmware waits a
period of time based on DRAM command timing specifications before issuing a new
command through the DCALCSR.
3.8.1.1
OCD EMRS Commands
FB DIMM DRAM timing is set up to work with OCD default calibration. Using the
DCALCSR and DCALADDR registers, EMRS OCD default and OCD exit commands can be
sent to the DRAMs.
Sending OCD EMRS drive(0), drive(1), or adjust DRAM commands may have
implementation dependent outcomes and should not be used in normal operation.
3.8.1.2
MRS Command Example
The following example shows how to send out an MRS command:
1. Write a value of 0x02320000 to the DCALADDR csr. This will configure the address/
bank bus for an MRS command with burst length 4, CAS latency 3, and write
recovery 2.
2. Write a value of 0x80000003 to the DCALCSR. This selects the (E)MRS command
mode and initiates the FSM that will issue the command.
3. Poll the DCALCSR until bit 31 is cleared to zero by hardware. This indicates that the
FSM has completed the selected operation.
3.8.2
DQS Failure CSR
The DQSFAIL CSR allows the AMB to calibrate properly even when one or more DQS
signals are missing, either through PCB or component failure. DQSFAIL is a 36 bit
register, one bit for each DQS pair of each rank. Software can set this CSR to force any
DQS signal to be excluded from the automatic DDR bus calibration. Hardware will also
detect missing DQS signals and automatically exclude them from calibration.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
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INTEL [ INTEL CORPORATION ]
