Registers
Device:
NodeID
Function: 1
Offset:
60h
Bit
Attr
Default
Description
VARLAT: Variable Read Latency Mode
10
RO
0
•
•
1 = Support Variable Read Latency on data returns
0 = Not supported
9
8
RO
RO
RO
RO
1
0
LAI: Logic Analyzer Interface Mode
•
•
1 = Support remapping DDR interface as Logic Analyzer Interface
0 = Not supported
DMASK: Data Mask for non-ECC Write Data
•
•
1 = Support data mask with non-ECC Write
0 = Not supported
7
0
L0S: Low Power Link State
•
•
1 = Support L0s state
0 = Not supported
6:2
1Eh
NBWC: Northbound Width Capability
•
•
•
•
1XXXX = 14 bits NB width supported
X1XXX = 14bits fail over to 13 bits mode supported.
XX1XX = 13 bits NB width supported
XXX1X = 13 bits fail over to 12 bits mode supported.
1:0
RO
01
SBWC: Southbound Width Capability
•
X1 = 10 SB bits: Device supports 10-bits and 10-bit fail-over to 9-bits.
Both configurations deliver 72-bits of data payload frame.
•
1X = Reserved
14.3.1.7
FBDLIS: FBD Link Initialization Status
This register reports FBD initialization status and is only valid when the link is up since
it is not sticky.
Device:
NodeID
Function: 1
Offset:
Bit
64h
Attr
Default
Description
31:20
19
RV
RO
0
0
Reserved
DATAMERGEERROR: NorthBound Data Merge Error
1 = NB merge error
•
18
ROST
0
NBMERGEDIS: NorthBound Merge Disable
Set by TS2 packet addressed to it
•
•
1 = Disable NB merge
Note: state in AMB should be sticky through fast link reset until new TS2
resets bit or hard pin reset
17:12
RO
3Fh
NBWCFG: Northbound width configuration set by TS3
•
•
See table in FBD Architecture & Protocol Specification for full decoding
[5:4] = Selects 14, 13 or 12 lane operation.
= Protocol Selection[1:0] out TS3 Protocol Selection[3:0]
[3:0] - Selects none or one lane to map out
•
= NB Channel Configuration [3:0] in TS3
11:8
7
RO
RV
Fh
0
SBWCFG: Southbound width capability set by TS3
•
•
See Table in FBD Architecture & Protocol Specification for full decoding
[3:0] - Selects none or one lane to map out
Reserved
Intel® 6400/6402 Advanced Memory Buffer Datasheet
173
INTEL [ INTEL ]
