Registers
Device:
NodeID
Function: 1
Offset:
40h
Att
r
Bit
Default
Description
3
RO
RO
0h
S3: Northbound Debug Event (1 = asserted, 0 = inactive): This bit is
used to communicate debug events to the host.
2:1
0h
S[2:1]: Thermal Trip: This field indicates various thermal conditions of
the AMB as follows:
•
•
•
•
00 – Below TEMPLO
01 – Above TEMPLO
10 – Above TEMPMID and falling
11 – Above TEMPMID and rising
The TEMPLO threshold is generally used to inform the host to accelerate
refresh events. The TEMPMID threshold is generally used to inform the
host that a thermal limit has been exceeded and that thermal throttling is
needed. Refer to the RAS chapter for more details on thermal
management.
0
RO
0h
S0: ERROR Asserted: This bit indicates an error has been detected by the
AMB. Errors can be alert or other type.
14.3.1.2
FBDS1: FBD Status 1
This register contains copies of status bits returned by the AMB in the most recent
northbound status frame when SYNC command R[1:0] field is 2’b01.
Device:
NodeID
Function: 1
Offset:
Bit
41h
Att
r
Default
Description
7:5
4
RV
RO
0h
0h
Reserved
SP: Parity: This bit contains an odd parity bit that covers the
S[3:0] field.
3:1
0
RV
RO
0h
0h
Reserved
S0: Data Merge Error: This bit indicates that the northbound
data merge alignment logic of an intermediate AMB cannot
met the timing required to merge its DRAM data into the
northbound data stream when required. Refer to the
initialization chapter for details.
14.3.1.3
FBDS2: FBD Status 2
This register contains copies of status bits returned by the AMB in the most recent
northbound status frame when SYNC command R[1:0] field is 2’b10.
Device:
NodeID
Function: 1
Offset:
Bit
42h
Att
r
Default
Description
7:5
4
RV
RO
0h
0h
Reserved
SP: Parity: This bit contains an odd parity bit that covers the
S[3:0] field.
3:0
RV
0h
Reserved
Intel® 6400/6402 Advanced Memory Buffer Datasheet
171
INTEL [ INTEL ]
