DDR MemBIST
11.3.2.4.6
Address Inversion for Vtt Balancing
FB-DIMMs use a separate termination (Vtt) power supply for command/address
termination. Keep in mind the AMB has two copies of the CA bus. In normal operation
the AMB attempts to balance the number of high and low address lines by inverting one
of the address ports. Inverting one copy of the addresses reduces Vtt power
consumption. This operation is invisible to the controller and DRAM, as this is simply a
static inversion of address lines.
By default this behavior is enabled for all memory accesses including during MemBIST
operation. Most memory test patterns assume a particular address sequence. Vtt
balancing might not be desirable in these cases. The AMB provides a control bit
(DRC.BALDIS) to turn off Vtt balancing if desired. If the bit is set, no balancing will take
place. If adjacent address inversion is disabled Vtt power may increase substantially,
placing additional load on the system power supply.
11.3.3
Memory Data Formatting
During MemBIST operation, 144-bit data is used to write to memory and to check data
read from memory. The data register MBDATA allows definition of a 144-bit data
pattern. The 144-bit data will be written in two consecutive 72-bit locations within a
memory burst. When operating with a burst length of 4 (BL4), early data is written to
the first and third locations in the burst and late data to the second and fourth
locations. An 8-word burst (BL8) is treated in similar manner, with early data written to
odd-numbered locations and late data to even locations.
11.3.3.1
Static Data Formats
MemBIST provides a number of static data patterns which can be selected using bits in
MBCSR. A static data pattern is one in which the data remains the same throughout
the MemBIST operation. One such static data format is the fixed data pattern. The
fixed data patterns are concatenated together multiple times to make up the number of
bits required supply data to the DRAMs. In addition to these fixed patterns, the
MBDATA registers can be used to supply 144 bits of user-defined data. The data from
this static pattern is also concatenated together multiple times to make up the required
number of bits for MemBIST use.
Finally, there are certain cases, such as initializing ECC bits in system memory, that
require unique data in each data word. This requirement is met by using all 288 bits of
the data register MBDATA for user-defined data. This usage of the data register for
user-defined data occupies bits which normally are used for failure information.
Because the registers normally used for failure information are occupied with the data
pattern, when 288-bit user-defined data is used, no checking is performed.
11.3.3.2
Dynamic Data Formats
In addition to the static data formats, MemBIST has the ability to provide dynamically
changing data patterns. Dynamic data changes each time that a new address is
accessed. These supply shifted data and pseudo-random data.
Note:
The following description of circular shift and LFSR random data generation describes
the Intel 6400/6402 Advanced Memory Buffer implementation. This does not match the
FBD DFx description of these functions. Resolution of these differences will be decided
based on potential changes to Intel 6400/6402 Advanced Memory Buffer.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
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INTEL [ INTEL ]
