DDR MemBIST
11.3.2.4.5
Dynamic Address Inversion (DAI):
Dynamic address inversion (DAI) is provided to maximize the switching of address lines
during testing. When dynamic address inversion is enabled, the address counters
increment or decrement as usual, but every other address driven to the DRAMs is the
logical inverse of the previous address used. The least significant address bit is not
inverted since it already toggles at the address rate.
All address lines (X, Y and Z) are inverted by DAI, creating a ping-pong access pattern.
This occurs in all address sequencing modes. This behavior might lead to accesses in
unexpected portions of the address space. For example, DAI inverts the bank address
lines even in Fast X, Fast Y and Fast XY modes, which normally have fixed bank
addresses. As a result, every other access is to a different bank than the fixed bank
selected by the addressing mode (either MB_START_ADDR:ba field or bank 0 for range
or full addressing respectively). Between each access, the old bank must be closed and
the new bank must be activated. In another example, with XZY address sequencing
and range addressing, it is normal to think of accesses as being restricted to the
address range specified in MB_START_ADDR and MB_END_ADDR. But with DAI
enabled, the non-inverted accesses will be within the specified range, but the inverted
accesses could possibly fall outside of the specified address range.
DAI can be used with any address sequencing mode. It can also be used with either
incrementing or decrementing addresses. Table 11-5 gives an example of both address
incrementing and address decrementing in DAI mode. This example is of XZY address
sequencing with range addressing and shows only low-order bank and column address
lines. Shaded rows are non-inverted, non-shaded rows show inverted addresses.
Table 11-5. Dynamic Address Inversion, XZY Address Sequencing and Range Addressing
Normal
Column
DAI, incrementing address
Bank Column
DAI, decrementing address
Bank Column
Bank
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
01
Etc.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
00
11
00
11
00
11
00
11
00
11
00
11
00
11
00
11
01
10
Etc.
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
00
11
00
11
00
11
00
11
00
11
00
11
00
11
00
11
11
00
Etc.
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
122
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
