DDR MemBIST
Figure 11-1. Range and Full Address Spaces
One Bank
Limit of address space as set by number of X and Y address lines
Address space as set by values in MTR register
Address space as set by start and end values in
MB_START_ADDR and MB_END_ADDR registers
E
S
Increasing X
0
0 Increasing Y
0001
As the figure above illustrates, when the values of the MB_START_ADDR (marked
S)
and MB_END_ADDR (marked
E)
registers are used to set the address space for a
MemBIST operation, the values in these registers must bear the correct relationship to
each other. The start address sets the lower bound for the test address space in both
the X and Y directions, and the end address sets the upper bound in both the X and Y
directions. For a start and end address to define a usable address space, it is required
that X
s
< X
e
, and Y
s
< Y
e
. In addition, when an address sequencing mode is chosen in
which the bank field in MB_END_ADDR is significant, it is also required that Z
s
< Z
e
. (If
a single physical address is to be tested, MBADDR, not MB_START_ADDR and
MB_END_ADDR, is used.)
In every case in which an address endpoint is specified using a register value,
MemBIST includes the address endpoint in the operation. For example, if an address
range is specified using the MB_START_ADDR and MB_END_ADDR registers, the
locations specified in these registers are included as part of the address range. The
MemBIST operation will be performed on both of the locations specified in these
registers.
11.3.2.3.1
Order and Direction of Address Sequencing
The order of sequencing through the test address space is chosen using the
MBCSR:fast field. The options are Fast Y (with fixed bank), Fast X (with fixed bank),
Fast XY (with fixed bank) and XZY. The terms Fast X, Fast Y, Fast XY and XZY refer to
the order in which addresses are incremented or decremented during MemBIST
execution. This order is given in
above as “counter order.” Counter order of
XZY, for example, indicates that the Y counter is counted most rapidly. When counter Y
over or underflows due to reaching the programmed limit of its count, the overflow or
Intel® 6400/6402 Advanced Memory Buffer Datasheet
117
INTEL [ INTEL CORPORATION ]
