Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
Name
Type
Description
DBI[3:0]# (Data Bus Inversion) are source synchronous and
indicate the polarity of the D[63:0]# signals.The DBI[3:0]# signals
are activated when the data on the data bus is inverted. If more
than half the data bits, within a 16-bit group, would have been
asserted electrically low, the bus agent may invert the data bus
signals for that particular sub-phase for that 16-bit group.
DBI[3:0] Assignment To Data Bus
Input/
Output
DBI[3:0]#
Bus Signal
Data Bus Signals
DBI3#
DBI2#
DBI1#
DBI0#
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
DBR# (Debug Reset) is used only in processor systems where no
debug port is implemented on the system board. DBR# is used by
DBR#
Output a debug port interposer so that an in-target probe can drive system
reset. If a debug port is implemented in the system, DBR# is a no
connect in the system. DBR# is not a processor signal.
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the processor FSB to indicate that the data bus is in
use. The data bus is released after DBSY# is de-asserted. This
signal must connect the appropriate pins/lands on all processor
Input/
Output
DBSY#
FSB agents.
DEFER# is asserted by an agent to indicate that a transaction
cannot be ensured in-order completion. Assertion of DEFER# is
DEFER#
DP[3:0]#
DRDY#
Input
normally the responsibility of the addressed memory or input/
output agent. This signal must connect the appropriate pins/lands
of all processor FSB agents.
DP[3:0]# (Data parity) provide parity protection for the D[63:0]#
Input/ signals. They are driven by the agent responsible for driving
Output D[63:0]#, and must connect the appropriate pins/lands of all
processor FSB agents.
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be de-asserted to insert idle
clocks. This signal must connect the appropriate pins/lands of all
Input/
Output
processor FSB agents.
DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
Signals
Associated Strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
Input/
Output
DSTBN[3:0]#
Datasheet
67
INTEL [ INTEL ]
