Electrical Specifications
2.7
Clock Specifications
2.7.1
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the Pentium 4 processor core
frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier
will be set at its default ratio during manufacturing. Refer to Table 17 for the processor
supported ratios.
The processor uses a differential clocking implementation. For more information on
processor clocking, contact your Intel representative.
Table 17.
Core Frequency to FSB Multiplier Configuration
Core Frequency
(200 MHz BCLK/
800 MHz FSB)
Multiplication of System Core
Frequency to FSB Frequency
Notes1,2
1/12
1/13
2.40 GHz
2.60 GHz
2.80 GHz
3 GHz
1/14
1/15
1/16
3.20 GHz
3.40 GHz
3.60 GHz
3.80 GHz
4 GHz
1/17
1/18
1/19
1/20
1/21
4.20 GHz
4.40 GHz
4.60 GHz
4.80 GHz
5 GHz
1/22
1/23
1/24
1/25
NOTES:
1. Individual processors operate only at or below the rated frequency.
2. Listed frequencies are not necessarily committed production frequencies.
Datasheet
29
INTEL [ INTEL ]
