Chapter 4: Hot Socketing and Power-On Reset in MAX V Devices
4–5
Power-On Reset Circuitry
When the I/O pin receives a negative ESD zap at the pin that is less than –0.7 V (0.7 V
is the voltage drop across a diode), the intrinsic
P-Substrate/N+ drain diode is forward biased. Therefore, the discharge ESD current
path is from GND to the I/O pin, as shown in Figure 4–4.
Figure 4–4. ESD Protection During Negative Voltage Zap
I/O
Source
D
Gate
PMOS
N+
Drain
Drain
P-Substrate
G
I/O
S
Gate
N+
NMOS
Source
GND
GND
Power-On Reset Circuitry
MAX V devices have POR circuits to monitor the VCCINT and VCCIO voltage levels
during power up. The POR circuit monitors these voltages, triggering download from
the non-volatile configuration flash memory block to the SRAM logic, maintaining the
tri-state of the I/O pins (with weak pull-up resistors enabled) before and during this
process. When the MAX V device enters user mode, the POR circuit releases the I/O
pins to user functionality. The POR circuit of the MAX V device does not monitor the
VCCINT voltage level after the device enters into user mode.
Power-Up Characteristics
When power is applied to a MAX V device, the POR circuit monitors VCCINT and
begins SRAM download at 1.55 V for MAX V devices. From this voltage reference, the
SRAM download and entry into user mode takes 200 to 450 µs maximum, depending
on your device density. This period of time is specified as tCONFIG in the power-up
timing section of the DC and Switching Characteristics for MAX V Devices chapter.
Entry into user mode is gated by whether all the VCCIO banks are powered with
sufficient operating voltage. If VCCINT and VCCIO are powered simultaneously, the
device enters user mode within the tCONFIG specifications. If VCCIO is powered more
than tCONFIG after VCCINT, the device does not enter user mode until 2 µs after all VCCIO
banks are powered.
December 2010 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
