Chapter 4: Hot Socketing and Power-On Reset in MAX V Devices
4–3
Hot-Socketing Feature Implementation in MAX V Devices
Hot-Socketing Feature Implementation in MAX V Devices
The hot-socketing feature tri-states the output buffer during the power-up event
(either the VCCINT or VCCIO power supplies) or power-down event. The hot-socketing
circuitry generates an internal HOTSCKTsignal when either VCCINT or VCCIO is below
the threshold voltage during power up or power down. The HOTSCKT signal cuts off
the output buffer to ensure that no DC current leaks through the pin (except for weak
pull-up leaking). When VCC ramps up very slowly during power up, VCC may still be
relatively low even after the POR signal is released and device configuration is
complete.
1
Ensure that VCCINT is within the recommended operating range even though SRAM
download has completed.
Figure 4–1 shows the circuitry for each I/O and clock pin.
Figure 4–1. Hot-Socketing Circuitry for MAX V Devices
Power On
Reset
Monitor
VCCIO
Weak
Pull-Up
Resistor
Output Enable
PAD
Voltage
Tolerance
Control
Hot Socket
Input Buffer
to Logic Array
The POR circuit monitors the VCCINT and VCCIO voltage levels and keeps the I/O pins
tri-stated until the device has completed its flash memory configuration of the SRAM
logic. The weak pull-up resistor (R) from the I/O pin to VCCIO is enabled during
download to keep the I/O pins from floating. The 3.3-V tolerance control circuit
permits the I/O pins to be driven by 3.3 V before VCCIO and/or VCCINT are powered,
and it prevents the I/O pins from driving out when the device is not fully powered or
operational. The hot-socketing circuitry prevents the I/O pins from internally
powering VCCIO and VCCINT when driven by external signals before the device is
powered.
f For more information about the 5.0-V tolerance, refer to the Using MAX V Devices in
Multi-Voltage Systems chapter.
December 2010 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
