2–32
Chapter 2: MAX V Architecture
I/O Structure
PCI Compliance
The MAX V 5M1270Z and 5M2210Z devices are compliant with PCI applications as
well as all 3.3-V electrical specifications in the PCI Local Bus Specification Revision 2.2.
These devices are also large enough to support PCI intellectual property (IP) cores.
Table 2–5 shows the MAX V device speed grades that meet the PCI timing
specifications.
Table 2–5. 3.3-V PCI Electrical Specifications and PCI Timing Support for MAX V Devices
Device
5M1270Z
5M2210Z
33-MHz PCI
All Speed Grades
All Speed Grades
LVDS and RSDS Channels
The MAX V device supports emulated LVDS and RSDS outputs on both row and
column I/O banks. You can configure the rows and columns as emulated LVDS or
RSDS output buffers that use two single-ended output buffers with three external
resistor networks.
Table 2–6. LVDS and RSDS Channels supported in MAX V Devices (Note 1)
Device
5M40Z
64 MBGA
10 eTx
10 eTx
—
64 EQFP
20 eTx
20 eTx
20 eTx
—
68 MBGA
—
100 TQFP 100 MBGA 144 TQFP
256 FBGA
—
324 FBGA
—
—
—
—
—
—
5M80Z
20 eTx
20 eTx
20 eTx
—
33 eTx
33 eTx
33 eTx
28 eTx
—
—
—
5M160Z
5M240Z
5M570Z
5M1270Z
5M2210Z
33 eTx
33 eTx
28 eTx
—
—
—
—
—
49 eTx
49 eTx
42 eTx
—
—
—
—
—
75 eTx
90 eTx
83 eTx
—
—
—
—
115 eTx
115 eTx
—
—
—
—
—
Note to Table 2–6:
(1) eTx = emulated LVDS output buffers (LVDS_E_3R) or emulated RSDS output buffers (RSDS_E_3R).
Schmitt Trigger
The input buffer for each MAX V device I/O pin has an optional Schmitt trigger
setting for the 3.3-V and 2.5-V standards. The Schmitt trigger allows input buffers to
respond to slow input edge rates with a fast output edge rate. Most importantly,
Schmitt triggers provide hysteresis on the input buffer, preventing slow-rising noisy
input signals from ringing or oscillating on the input signal driven into the logic array.
This provides system noise tolerance on MAX V inputs, but adds a small, nominal
input delay.
The JTAG input pins (TMS, TCK, and TDI) have Schmitt trigger buffers that are always
enabled.
1
The TCKinput is susceptible to high pulse glitches when the input signal fall time is
greater than 200 ns for all I/O standards.
MAX V Device Handbook
December 2010 Altera Corporation
INTEL [ INTEL ]
