Chapter 2: MAX V Architecture
2–19
Global Signals
Global Signals
Each MAX V device has four dual-purpose dedicated clock pins (GCLK[3..0], two
pins on the left side and two pins on the right side) that drive the global clock network
for clocking, as shown in Figure 2–13. These four pins can also be used as GPIOs if
they are not used to drive the global clock network.
The four global clock lines in the global clock network drive throughout the entire
device. The global clock network can provide clocks for all resources within the
device including LEs, LAB local interconnect, IOEs, and the UFM block. The global
clock lines can also be used for global control signals, such as clock enables,
synchronous or asynchronous clears, presets, output enables, or protocol control
signals such as TRDYand IRDYfor the PCI I/O standard. Internal logic can drive the
global clock network for internally-generated global clocks and control signals.
Figure 2–13 shows the various sources that drive the global clock network.
Figure 2–13. Global Clock Generation
GCLK0
GCLK1
GCLK2
4
Global Clock
Network
GCLK3
4
Logic Array(1)
Note to Figure 2–13:
(1) Any I/O pin can use a MultiTrack interconnect to route as a logic array-generated global clock signal.
The global clock network drives to individual LAB column signals, LAB column
clocks [3..0], that span an entire LAB column from the top to the bottom of the
device. Unused global clocks or control signals in an LAB column are turned off at the
LAB column clock buffers shown in Figure 2–14. The LAB column clocks [3..0]are
multiplexed down to two LAB clock signals and one LAB clear signal. Other control
signal types route from the global clock network into the LAB local interconnect. For
more information, refer to “LAB Control Signals” on page 2–6.
December 2010 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
