8–4
Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
IEEE Std. 1149.1 Boundary-Scan Register
Figure 8–3 shows how test data is serially shifted around the periphery of the IEEE
Std. 1149.1 device.
Figure 8–3. Boundary-Scan Register
Each peripheral
element is either an
I/O pin, dedicated
input pin, or
Internal Logic
dedicated
configuration pin.
TAP Controller
TDI
TMS
TDO
TCK
Boundary-Scan Cells of a MAX V Device I/O Pin
Except for the four JTAG pins and power pins, you can use all the pins of a MAX V
device (including clock pins) as user I/O pins and have a BSC. The 3-bit BSC consists
of a set of capture registers and a set of update registers. The capture registers can
connect to internal device data through the OUTJand OEJsignals, while the update
registers connect to external data through the PIN_OUTand PIN_OEsignals. The TAP
controller internally generates the SHIFT CLOCK, and UPDATEglobal control signals for
,
the IEEE Std. 1149.1 BST registers; a decode of the instruction register generates the
MODEsignal. The data signal path for the boundary-scan register runs from the serial
data in (SDI) signal to the serial data out (SDO) signal. The scan register begins at the
TDIpin and ends at the TDOpin of the device.
MAX V Device Handbook
December 2010 Altera Corporation
INTEL [ INTEL ]
