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5M80ZE64I5N 参数 Datasheet PDF下载

5M80ZE64I5N图片预览
型号: 5M80ZE64I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, 64-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用:
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
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Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices  
8–3  
IEEE Std. 1149.1 Boundary-Scan Register  
Figure 8–2 shows a functional model of the IEEE Std. 1149.1 circuitry.  
Figure 8–2. IEEE Std. 1149.1 Circuitry  
Instruction Register  
TDI  
TDO  
UPDATEIR  
CLOCKIR  
SHIFTIR  
Instruction Decode  
TAP  
TMS  
TCK  
Controller  
Data Registers  
Bypass Register  
UPDATEDR  
CLOCKDR  
SHIFTDR  
Boundary-Scan Register (1)  
Device ID Register  
ISP Registers  
Note to Figure 8–2:  
(1) For the boundary-scan register length in MAX V devices, refer to the JTAG and In-System Programmability in MAX V Devices chapter.  
The TAP controller controls the IEEE Std. 1149.1 boundary-scan testing, as described  
in “IEEE Std. 1149.1 BST Operation Control” on page 8–6. The TMSand TCKpins  
operate the TAP controller and the TDIand TDOpins provide the serial path for the  
data registers. The TDIpin also provides data to the instruction register, which then  
generates the control logic for the data registers.  
IEEE Std. 1149.1 Boundary-Scan Register  
The boundary-scan register is a large serial shift register that uses the TDIpin as an  
input and the TDOpin as an output. The boundary-scan register consists of 3-bit  
peripheral elements that are associated with the I/O pins of the MAX V devices. You  
can use the boundary-scan register to test the external pin connections or to capture  
internal data.  
December 2010 Altera Corporation  
MAX V Device Handbook  
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