7–8
Chapter 7: User Flash Memory in MAX V Devices
UFM Operating Modes
This megafunction is in the I/O folder on page 2a of the MegaWizard Plug-In
Manager. On page 3 of the MAX II/MAX V Oscillator megafunction, you have an
option to choose to simulate the OSCoutput port at its maximum or minimum
frequency during the design simulation. The frequency chosen is only used as a
timing parameter simulation and does not affect the real MAX V device OSCoutput
frequency.
UFM Operating Modes
There are three different modes for the UFM block:
■
■
■
Read/Stream Read
Program (Write)
Erase
During program mode, address and data can be loaded concurrently. You can
manipulate the UFM interface controls as necessary to implement the specific
protocol provided the UFM timing specifications are met. Figure 7–5 through
Figure 7–8 show the control waveforms for accessing UFM in three different modes.
For program mode (Figure 7–7) and erase mode (Figure 7–8), the PROGRAMand ERASE
signals can be asserted anytime after the address register and data register have been
loaded. Do not assert the READ
into the UFM after entering the real-time ISP mode. You can use the RTP
,
PROGRAM, and ERASEsignals or shift data and address
BUSYsignal to
_
detect the beginning and end of real-time ISP operation and generate control logic to
stop all UFM port operations. This user-generated control logic is only necessary for
the ALTUFM_NONE megafunction, which provides no auto-generated logic. The
other interfaces for the ALTUFM megafunction (ALTUFM_PARALLEL,
ALTUFM_SPI, ALTUFM_I2C) contain control logic to automatically monitor the
RTP_BUSYsignal and will cease operations to the UFM when a real-time ISP operation
is in progress.
1
You can program the UFM or CFM block independently without overwriting the
other block, which is not programmed. The Quartus II programmer provides the
options to program the UFM and CFM blocks individually or together (the entire
MAX V Device).
f For guidelines about using ISP and real-time ISP while using the UFM block within
your design, refer to AN 100: In-System Programmability Guidelines.
f For a complete description of the device architecture, and for the specific values of the
timing parameters listed in this chapter, refer to the MAX V Device Architecture
chapter.
MAX V Device Handbook
January 2011 Altera Corporation
INTEL [ INTEL ]
