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5M570ZF256C5N 参数 Datasheet PDF下载

5M570ZF256C5N图片预览
型号: 5M570ZF256C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 17.7ns, 440-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256]
分类和应用: 时钟LTEPC可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
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Chapter 2: MAX V Architecture  
2–3  
Functional Description  
Table 2–1 lists the number of LAB rows and columns in each device, as well as the  
number of LAB rows and columns adjacent to the flash memory area. The long LAB  
rows are full LAB rows that extend from one side of row I/O blocks to the other. The  
short LAB rows are adjacent to the UFM block; their length is shown as width in LAB  
columns.  
Table 2–1. Device Resources for MAX V Devices  
LAB Rows  
Device  
5M40Z  
UFM Blocks  
LAB Columns  
Total LABs  
Long LAB Rows  
Short LAB Rows (Width) (1)  
1
1
1
1
1
1
1
1
1
6
6
4
4
24  
24  
5M80Z  
5M160Z  
6
4
24  
5M240Z (2)  
5M240Z (3)  
5M570Z  
6
4
24  
12  
12  
16  
20  
20  
4
3 (3)  
3 (3)  
3 (5)  
3 (7)  
3 (7)  
57  
4
57  
5M1270Z (4)  
5M1270Z (5)  
5M2210Z  
7
127  
221  
221  
10  
10  
Notes to Table 2–1:  
(1) The width is the number of LAB columns in length.  
(2) Not applicable to T144 package of the 5M240Z device.  
(3) Only applicable to T144 package of the 5M240Z device.  
(4) Not applicable to F324 package of the 5M1270Z device.  
(5) Only applicable to F324 package of the 5M1270Z device.  
December 2010 Altera Corporation  
MAX V Device Handbook  
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