Chapter 3: DC and Switching Characteristics for MAX V Devices
3–13
Timing Model and Specifications
Table 3–18. LE Internal Timing Microparameters for MAX V Devices (Part 2 of 2)
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z
5M1270Z/ 5M2210Z
C4 C5, I5
Symbol
Parameter
Unit
C4
C5, I5
Min
253
—
Max
—
Min
339
—
Max
Min
216
—
Max
—
Min
266
—
Max
Minimum clock high or
low time
tCLKHL
tC
—
—
ps
ps
Register control delay
1,356
1,741
1,114
1,372
Table 3–19. IOE Internal Timing Microparameters for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z
5M1270Z/ 5M2210Z
C4 C5, I5
Symbol
Parameter
Unit
C4
C5, I5
Min
Max
Min
Max
Min
Max
Min
Max
Data output delay from
adjacent LE to I/O block
tFASTIO
tIN
—
170
—
428
—
207
—
254
ps
ps
I/O input pad and buffer
delay
—
—
907
—
—
986
—
—
920
—
—
1,132
2,430
I/O input pad and buffer
tGLOB (1) delay used as global
2,261
3,322
1,974
ps
signal pin
Internally generated
tIOE
—
—
—
530
318
—
—
—
1,410
509
—
—
—
374
291
—
—
—
460
358
ps
ps
ps
output enable delay
tDL
Input routing delay
Output delay buffer and
pad delay
tOD (2)
1,319
1,543
1,383
1,702
Output buffer disable
delay
tXZ (3)
tZX (4)
—
—
1,045
1,160
—
—
1,276
1,353
—
—
982
—
—
1,209
1,604
ps
ps
Output buffer enable
delay
1,303
Notes to Table 3–19:
(1) Delay numbers for tGLOB differ for each device density and speed grade. The delay numbers for tGLOB, shown in Table 3–19, are based on a 5M240Z
device target.
(2) For more information about delay adders associated with different I/O standards, drive strengths, and slew rates, refer to Table 3–34 on page 3–24
and Table 3–35 on page 3–25.
(3) For more information about tXZ delay adders associated with different I/O standards, drive strengths, and slew rates, refer to Table 3–22 on
page 3–15 and Table 3–23 on page 3–15.
(4) For more information about tZX delay adders associated with different I/O standards, drive strengths, and slew rates, refer to Table 3–20 on
page 3–14 and Table 3–21 on page 3–14.
May 2011 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
