Chapter 3: DC and Switching Characteristics for MAX V Devices
3–11
Timing Model and Specifications
Preliminary and Final Timing
This section describes the performance, internal, external, and UFM timing
specifications. All specifications are representative of the worst-case supply voltage
and junction temperature conditions.
Timing models can have either preliminary or final status. The Quartus II software
issues an informational message during the design compilation if the timing models
are preliminary. Table 3–16 lists the status of the MAX V device timing models.
Preliminary status means the timing model is subject to change. Initially, timing
numbers are created using simulation results, process data, and other known
parameters. These tests are used to make the preliminary numbers as close to the
actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing. These
numbers reflect the actual performance of the device under the worst-case voltage
and junction temperature conditions.
Table 3–16. Timing Model Status for MAX V Devices
Device
5M40Z
Final
v
5M80Z
v
5M160Z
5M240Z
5M570Z
5M1270Z
5M2210Z
v
v
v
v
v
Performance
Table 3–17 lists the MAX V device performance for some common designs. All
performance values were obtained with the Quartus II software compilation of
megafunctions.
Table 3–17. Device Performance for MAX V Devices (Part 1 of 2)
Performance
Resources Used
5M40Z/ 5M80Z/ 5M160Z/
Resource
Used
Design Size and
Function
5M1270Z/ 5M2210Z
5M240Z/ 5M570Z
Unit
UFM
Blocks
Mode
LEs
C4
C5, I5
C4
C5, I5
16-bit counter (1)
64-bit counter (1)
16-to-1 multiplexer
32-to-1 multiplexer
16-bit XORfunction
—
—
—
—
—
16
64
11
24
5
0
0
0
0
0
184.1
83.2
17.4
12.5
9.0
118.3
80.5
20.4
25.3
16.1
247.5
154.8
8.0
201.1
125.8
9.3
MHz
MHz
ns
LE
9.0
11.4
8.2
ns
6.6
ns
16-bit decoder with
single address line
—
5
0
9.2
16.1
6.6
8.2
ns
May 2011 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
