欢迎访问ic37.com |
会员登录 免费注册
发布采购

5M160ZE64C4N 参数 Datasheet PDF下载

5M160ZE64C4N图片预览
型号: 5M160ZE64C4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 7.9ns, 128-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 3966 K
品牌: INTEL [ INTEL ]
 浏览型号5M160ZE64C4N的Datasheet PDF文件第7页浏览型号5M160ZE64C4N的Datasheet PDF文件第8页浏览型号5M160ZE64C4N的Datasheet PDF文件第9页浏览型号5M160ZE64C4N的Datasheet PDF文件第10页浏览型号5M160ZE64C4N的Datasheet PDF文件第12页浏览型号5M160ZE64C4N的Datasheet PDF文件第13页浏览型号5M160ZE64C4N的Datasheet PDF文件第14页浏览型号5M160ZE64C4N的Datasheet PDF文件第15页  
Chapter 1: MAX V Device Family Overview  
1–3  
Integrated Software Platform  
the necessary power pins for migration. For I/O pin migration across densities, cross  
reference the available I/O pins using the device pin-outs for all planned densities of  
a given package type to identify which I/O pins can be migrated. The Quartus® II  
software can automatically cross-reference and place all pins for you when given a  
device migration list.  
Table 1–2. MAX V Packages and User I/O Pins (Note 1)  
64-Pin  
MBGA  
64-Pin  
EQFP  
68-Pin  
MBGA  
100-Pin  
TQFP  
100-Pin  
MBGA  
144-Pin  
TQFP  
256-Pin  
FBGA  
324-Pin  
FBGA  
Device  
5M40Z  
30  
30  
54  
54  
54  
52  
52  
52  
79  
79  
79  
74  
79  
79  
74  
5M80Z  
5M160Z  
5M240Z  
114  
114  
114  
5M570Z  
159  
211  
203  
5M1270Z  
5M2210Z  
Note to Table 1–2:  
271  
271  
(1) Device packages under the same arrow sign have vertical migration capability.  
Table 1–3. MAX V Package Sizes  
64-Pin  
MBGA  
64-Pin  
EQFP  
68-Pin  
MBGA  
100-Pin  
TQFP  
100-Pin  
MBGA  
144-Pin  
TQFP  
256-Pin  
FBGA  
324-Pin  
FBGA  
Package  
Pitch (mm)  
Area (mm2)  
0.5  
0.4  
81  
0.5  
25  
0.5  
0.5  
36  
0.5  
1
1
20.25  
256  
484  
289  
361  
Length × width  
(mm × mm)  
4.5 × 4.5  
9 × 9  
5 × 5  
16 × 16  
6 × 6  
22 × 22  
17 × 17  
19 × 19  
Integrated Software Platform  
The Quartus II software provides an integrated environment for HDL and schematic  
design entry, compilation and logic synthesis, full simulation and advanced timing  
analysis, and programming of MAX V devices.  
f For more information about the Quartus II software features, refer to the Quartus II  
Handbook.  
You can debug your MAX V designs using In-System Sources and Probes Editor in  
the Quartus II software. This feature allows you to easily control any internal signal  
and provides you with a completely dynamic debugging environment.  
f For more information about the In-System Sources and Probes Editor, refer to the  
Design Debugging Using In-System Sources and Probes chapter of the Quartus II  
Handbook.  
Device Pin-Outs  
f For more information, refer to the MAX V Device Pin-Out Files page.  
May 2011 Altera Corporation  
MAX V Device Handbook  
 复制成功!