6–8
Chapter 6: JTAG and In-System Programmability in MAX V Devices
In-System Programmability
behavior during the ISP sequence. The in-system programming clamp instruction
allows the device to sample and sustain the value on an output pin (an input pin
remains tri-stated if sampled) or to set a logic high, logic low, or tri-state value
explicitly on any pin. Setting these options is controlled on an individual pin basis
with the Quartus II software.
f For more information, refer to AN 630: Real-Time ISP and ISP Clamp for Altera CPLDs.
Real-Time ISP
For systems that require more than the DC logic level control of I/O pins, the
real-time ISP feature allows you to update the CFM block with a new design image,
while the current design continues to operate in the SRAM logic array and I/O pins.
A new programming file is updated into the MAX V device without halting the
original operation of your design, saving down-time costs for remote or field
upgrades. The updated CFM block configures the new design into the SRAM after the
next power cycle. You can execute an immediate SRAM configuration without a
power cycle with a specific sequence of ISP commands. The SRAM configuration
without a power cycle takes a specific amount of time (tCONFIG). During this time, the
I/O pins are tri-stated and weakly pulled-up to VCCIO
.
Design Security
All MAX V devices contain a programmable security bit that controls access to the
data programmed into the CFM block. If this bit is programmed, you cannot copy or
retrieve the design programming information stored in the CFM block. This feature
provides a high-level design security because programmed data within flash memory
cells is invisible. You can only reset the security bit that controls this function and
other programmed data if the device is erased. The SRAM is also invisible and cannot
be accessed regardless of the security bit setting. The security bit does not protect the
UFM block data, and the UFM is accessible through JTAG or logic array connections.
Programming with External Hardware
You can program MAX V devices by downloading the information through in-circuit
testers, embedded processors, the Altera® ByteBlaster™ II, EthernetBlaster II,
EthernetBlaster, and USB-Blaster™ cables. You need to power up these cable’s
VCC(TRGT) with VCCIO of Bank 1.
f For more information about the respective cables, refer to the Cable & Adapter
Drivers Information page.
BP Microsystems, System General, and other programming hardware manufacturers
provide programming support for Altera devices. For device support information,
refer to their websites.
MAX V Device Handbook
May 2011 Altera Corporation
INTEL [ INTEL ]
