Chapter 6: JTAG and In-System Programmability in MAX V Devices
6–7
In-System Programmability
A stand-alone verification of a programmed pattern involves only steps 1, 2, 5, and 6.
These steps are automatically executed by third-party programmers, the Quartus II
software, or the Jam STAPL and Jam Byte-Code Players.
Table 6–4 lists the programming times for MAX V devices with in-circuit testers to
execute the algorithm vectors in hardware. Because of data processing and data
transfer limitations, software-based programming tools used with download cables
are slightly slower.
Table 6–4. Family Programming Times for MAX V Devices
5M40Z/
5M80Z/
5M160Z/
5M240Z (1)
5M240Z
Description
5M570Z 5M1270Z (3) 5M1270Z (4) 5M2210Z Unit
(2)
Erase + Program (1 MHz)
Erase + Program (10 MHz)
Verify (1 MHz)
1.72
1.65
0.09
0.01
1.81
1.66
2.16
1.99
0.17
0.02
2.33
2.01
2.16
1.99
0.17
0.02
2.33
2.01
2.90
2.58
0.30
0.03
3.20
2.61
3.92
3.40
0.49
0.05
4.41
3.45
3.92
3.40
0.49
0.05
4.41
3.45
sec
sec
sec
sec
sec
sec
Verify (10 MHz)
Complete Program Cycle (1 MHz)
Complete Program Cycle (10 MHz)
Notes to Table 6–4:
(1) Not applicable to T144 package of the 5M240Z device.
(2) Only applicable to T144 package of the 5M240Z device.
(3) Not applicable to F324 package of the 5M1270Z device.
(4) Only applicable to F324 package of the 5M1270Z device.
User Flash Memory Programming
The Quartus II software (with the use of .pof, .jam, or .jbc files) supports
programming of the UFM block independent of the logic array design pattern stored
in the CFM block. This allows updating or reading UFM contents through ISP without
altering the current logic array design, or vice versa. By default, these programming
files and methods program the entire flash memory contents, which includes the CFM
block and UFM contents. The stand-alone embedded Jam STAPL Player and Jam
Byte-Code Player provide action commands for programming or reading the entire
flash memory (UFM and CFM together) or each independently.
f For more information, refer to AN 425: Using the Command-Line Jam STAPL Solution for
Device Programming.
In-System Programming Clamp
By default, the IEEE 1532 instruction used for entering ISP automatically tri-states all
I/O pins with weak pull-up resistors for the duration of the ISP sequence. However,
some systems may require certain pins on MAX V devices to maintain a specific DC
logic level during an in-field update. For these systems, you can use the optional in-
system programming clamp instruction in the MAX V circuitry to control I/O
May 2011 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
