5CSXFC5C6U23C7N 参数 Datasheet PDF下载

型号：	5CSXFC5C6U23C7N
PDF下载：	下载PDF文件查看货源
内容描述：	[Field Programmable Gate Array, 85000-Cell, CMOS, PBGA672, ROHS COMPLIANT, UBGA-672]
分类和应用：	栅可编程逻辑
文件页数/大小：	66 页 / 1360 K
品牌：	INTEL [ INTEL ]

Switching Characteristics

Page 17

Table 20. Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices (Part 2 of 4)

Transceiver

Speed Grade 7

Speed Grade 5 ⁽¹⁾

Speed Grade 6

Symbol/

Description

Conditions

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

2000

R_REF

—

Transceiver Clocks

fixedclk clock

frequency

PCIe

Receiver Detect

—

125

—

125

—

125

—

MHz

Transceiver

Reconfiguration

Controller IP

100/

—

125 ⁽⁷⁾

(mgmt_clk_clk) clock

frequency

Receiver

Supported I/O

Standards

1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS

5000/

Data rate ⁽¹⁶⁾

—

614

—

614

—

3125

1.2

614

—

2500

1.2

Mbps

6144 ⁽⁶⁾

Absolute V_MAXfor a

receiver pin ⁽⁸⁾

1.2

Absolute V_MINfor a

receiver pin

–0.4

—

–0.4

—

–0.4

—

Maximum peak-to-peak

differentialinputvoltage

—

1.6

—

1.6

2.2

—

1.6

2.2

—

V_ID(diff p-p) before

device configuration

Maximum peak-to-peak

differentialinputvoltage

2.2

—

V_ID(diff p-p) after

device configuration

Minimum differential

eye opening at the

receiver serial input

110

(9)

pins

85−Ω setting

100−Ω setting

120−Ω setting

150-Ω setting

—

100

120

150

100

120

150

100

120

150

Differential on-chip

termination resistors

2.5 V PCML,

LVPECL, and

LVDS

_{CCE_GXBL}supply ^{(5), (6)}

V_{CCE_GXBL}supply

0.65 ⁽¹⁵⁾/0.8

V_{CCE_GXBL}supply

V_ICM(AC coupled)

1.5 V PCML

(10)

t_LTR

—

µs

(11)

t_LTD

—

(12)

t_{LTD_manual}

July 2014 Altera Corporation

Cyclone V Device Datasheet

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