Cyclone V Device Datasheet
CV-51002 | 2019.01.25
Table 22.
Transceiver Clocks Specifications for Cyclone V GX, GT, SX, and ST Devices
Symbol/Description
Condition
Transceiver Speed Grade 5(30)
Transceiver Speed Grade 6
Transceiver Speed Grade 7
Unit
Min
—
Typ
125
—
Max
Min
—
Typ
125
—
Max
Min
—
Typ
125
—
Max
PCIe Receiver Detect
—
—
—
—
MHz
MHz
fixedclk clock frequency
Transceiver Reconfiguration
Controller IP
75
100/125(3
75
100/125(
75
100/125(3
7)
37)
7)
(mgmt_clk_clk) clock
frequency
Table 23.
Receiver Specifications for Cyclone V GX, GT, SX, and ST Devices
Symbol/Description
Condition
Transceiver Speed Grade 5(30)
Transceiver Speed Grade 6
Min Typ Max
1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
Transceiver Speed Grade 7
Unit
Min
Typ
Max
Min
Typ
Max
Supported I/O standards
Data rate(38)
—
—
—
—
614
—
—
—
—
—
5000/614
4(35)
614
—
—
—
—
3125
1.2
—
614
—
—
—
—
—
2500
1.2
—
Mbps
Absolute VMAX for a receiver
pin(39)
1.2
—
V
V
V
Absolute VMIN for a receiver
pin
–0.4
—
—
–0.4
—
–0.4
—
Maximum peak-to-peak
differential input voltage
VID (diff p-p) before device
configuration
1.6
1.6
1.6
Maximum peak-to-peak
differential input voltage
VID (diff p-p) after device
configuration
—
—
—
2.2
—
—
2.2
—
—
2.2
V
continued...
(37)
The maximum supported clock frequency is 100 MHz if the PCIe hard IP block is enabled or 125 MHz if the PCIe hard IP block is not
enabled.
(38)
(39)
To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
The device cannot tolerate prolonged operation at this absolute maximum.
Cyclone V Device Datasheet
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