Cyclone V Device Datasheet
CV-51002 | 2019.01.25
Transceiver Performance Specifications
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices
Table 21.
Reference Clock Specifications for Cyclone V GX, GT, SX, and ST Devices
Symbol/Description
Condition
Transceiver Speed Grade 5(30)
Transceiver Speed Grade 6
Transceiver Speed Grade 7
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Supported I/O standards
1.2 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL(31), HCSL, and LVDS
Input frequency from
—
27
—
—
—
—
—
550
400
400
27
—
—
—
—
—
550
400
400
27
—
—
—
—
—
550
400
400
MHz
ps
REFCLK input pins(32)
Rise time
Measure at ±60 mV of
differential signal(33)
Fall time
Measure at ±60 mV of
differential signal(33)
ps
Duty cycle
—
—
45
—
—
55
45
—
—
55
45
—
—
55
%
Peak-to-peak differential
input voltage
200
2000
200
2000
200
2000
mV
Spread-spectrum
modulating clock frequency
PCIe
PCIe
—
30
—
—
—
33
—
—
30
—
—
—
33
—
—
30
—
—
—
33
—
—
kHz
—
Spread-spectrum
downspread
0 to –
0.5%
0 to –
0.5%
0 to –
0.5%
On-chip termination
resistors
100
100
100
Ω
continued...
(30)
(31)
Transceiver Speed Grade 5 covers specifications for Cyclone V GT and ST devices.
Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this
table.
(32)
(33)
The reference clock frequency must be ≥ 307.2 MHz to be fully compliance to CPRI transmit jitter specification at 6.144 Gbps. For
more information about CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
REFCLK performance requires to meet transmitter REFCLK phase noise specification.
Cyclone V Device Datasheet
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