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5ASTFD5K3F40I3N 参数 Datasheet PDF下载

5ASTFD5K3F40I3N图片预览
型号: 5ASTFD5K3F40I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA1517, ROHS COMPLIANT, FBGA-1517]
分类和应用: 可编程逻辑
文件页数/大小: 122 页 / 2542 K
品牌: INTEL [ INTEL ]
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Electrical Characteristics  
Page 13  
Table 14. Single-Ended I/O Standards for Arria V Devices (Part 2 of 2)  
VCCIO (V)  
Typ  
VIL (V)  
Max  
VIH (V)  
VOL (V)  
Max  
VOH (V)  
Min  
(1)  
(1)  
IOL  
IOH  
I/O Standard  
(mA) (mA)  
Min  
Max  
Min  
Min  
Max  
0.65 x  
VCCIO  
1.2 V  
1.14  
1.2  
1.26  
–0.3 0.35 x VCCIO  
VCCIO + 0.3 0.25 x VCCIO 0.75 x VCCIO  
2
–2  
Note to Table 14:  
(1) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the 3.3-V LVTTL specification (4 mA), you  
should set the current strength settings to 4 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the handbook.  
Table 15. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Arria V Devices  
VCCIO(V)  
Typ  
VREF(V)  
Typ  
VTT(V)  
Typ  
I/O Standard  
Min  
Max  
Min  
Max  
Min  
Max  
SSTL-2  
Class I, II  
2.375  
2.5  
1.8  
2.625  
0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO  
0.833 0.9 0.969  
VREF – 0.04  
VREF  
VREF  
VREF + 0.04  
SSTL-18  
Class I, II  
1.71  
1.425  
1.283  
1.19  
1.89  
1.575  
1.418  
1.26  
V
REF – 0.04  
VREF + 0.04  
SSTL-15  
Class I, II  
1.5  
0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO  
0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO  
0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO  
0.5 x VCCIO 0.51 x VCCIO  
0.5 x VCCIO 0.51 x VCCIO  
0.5 x VCCIO 0.51 x VCCIO  
SSTL-135  
Class I, II  
1.35  
1.25  
1.8  
SSTL-125  
Class I, II  
HSTL-18  
Class I, II  
1.71  
1.89  
0.85  
0.68  
0.9  
0.95  
0.9  
VCCIO/2  
CCIO/2  
HSTL-15  
Class I, II  
1.425  
1.5  
1.575  
0.75  
V
HSTL-12  
Class I, II  
1.14  
1.14  
1.2  
1.2  
1.26  
1.3  
0.47 x VCCIO 0.5 x VCCIO 0.53 x VCCIO  
0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO  
VCCIO/2  
HSUL-12  
Table 16. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Arria V Devices (Part 1 of 2)  
VIL(DC) (V)  
VIH(DC) (V)  
Min Max  
VREF  
VIL(AC) (V) VIH(AC) (V)  
Max Min  
VOL (V)  
Max  
VOH (V)  
Min  
(1)  
(1)  
Iol  
Ioh  
I/O Standard  
(mA)  
8.1  
16.2  
6.7  
13.4  
8
(mA)  
–8.1  
–16.2  
–6.7  
–13.4  
–8  
Min  
Max  
SSTL-2  
Class I  
VREF  
–0.15  
+
VCCIO  
0.3  
+
+
+
+
VREF  
0.31  
–0.3  
VREF + 0.31 VTT – 0.608 VTT + 0.608  
VREF + 0.31 VTT – 0.81 VTT + 0.81  
VREF + 0.25 VTT – 0.603 VTT + 0.603  
0.15  
SSTL-2  
Class II  
VREF  
–0.15  
VREF  
0.15  
+
VCCIO  
0.3  
VREF  
0.31  
–0.3  
–0.3  
–0.3  
SSTL-18  
Class I  
VREF  
–0.125  
VREF  
0.125  
+
VCCIO  
0.3  
VREF  
0.25  
SSTL-18  
Class II  
VREF  
–0.125  
VREF  
0.125  
+
VCCIO  
0.3  
VREF  
0.25  
VREF + 0.25  
VREF  
0.28  
VCCIO –0.28  
0.8 x VCCIO  
0.8 x VCCIO  
SSTL-15  
Class I  
VREF  
0.1  
VREF  
0.1  
+
+
VREF  
+
0.2 x VCCIO  
0.2 x VCCIO  
0.175  
0.175  
SSTL-15  
Class II  
VREF  
0.1  
VREF  
0.1  
VREF  
0.175  
VREF  
0.175  
+
16  
–16  
December 2013 Altera Corporation  
Arria V GX, GT, SX, and ST Device Datasheet