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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
1-16  
I/O Standard Specifications  
Table 1-13: Internal Weak Pull-Up Resistor Values for Arria V Devices  
Symbol  
Description  
Condition (V)(11)  
Value(12)  
25  
Unit  
kΩ  
kΩ  
kΩ  
kΩ  
kΩ  
kΩ  
kΩ  
kΩ  
VCCIO = 3.3 5%  
VCCIO = 3.0 5%  
VCCIO = 2.5 5%  
VCCIO = 1.8 5%  
VCCIO = 1.5 5%  
VCCIO = 1.35 5%  
VCCIO = 1.25 5%  
VCCIO = 1.2 5%  
25  
25  
Value of the I/O pin pull-up resistor before and during  
configuration, as well as user mode if you have enabled the  
programmable pull-up resistor option.  
25  
RPU  
25  
25  
25  
25  
Related Information  
Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines  
Provides more information about the pins that support internal weak pull-up and internal weak pull-down features.  
I/O Standard Specifications  
Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various  
I/O standards supported by Arria V devices.  
You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.  
(11)  
(12)  
Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO  
Valid with 10% tolerances to cover changes over PVT.  
.
Arria V GX, GT, SX, and ST Device Datasheet  
Send Feedback  
Altera Corporation  
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