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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
2-14  
Hot Socketing  
Hot Socketing  
Table 2-14: Hot Socketing Specifications for Arria V GZ Devices  
Symbol  
Description  
Maximum  
300 μA  
IIOPIN (DC)  
DC current per I/O pin  
IIOPIN (AC)  
AC current per I/O pin  
8 mA (123)  
100 mA  
50 mA  
IXCVR-TX (DC)  
IXCVR-RX (DC)  
DC current per transceiver transmitter pin  
DC current per transceiver receiver pin  
Internal Weak Pull-Up Resistor  
Table 2-15: Internal Weak Pull-Up Resistor for Arria V GZ Devices  
All I/O pins have an option to enable the weak pull-up resistor except the configuration, test, and JTAG pins. The internal weak pull-down feature is only  
available for the JTAG TCKpin. The typical value for this internal weak pull-down resistor is approximately 25 kΩ .  
Symbol  
Description  
VCCIO Conditions (V) (124)  
Value (125)  
Unit  
k Ω  
k Ω  
k Ω  
kΩ  
3.0 5%  
25  
25  
25  
25  
25  
25  
25  
2.5 5%  
1.8 5%  
1.5 5%  
1.35 5%  
1.25 5%  
1.2 5%  
Value of the I/O pin pull-up resistor  
before and during configuration, as well  
as user mode if you enable the  
RPU  
programmable pull-up resistor option.  
k Ω  
k Ω  
k Ω  
(123)  
The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew  
rate.  
(124)  
(125)  
The pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO  
These specifications are valid with a 10% tolerance to cover changes over PVT.  
.
Arria V GZ Device Datasheet  
Send Feedback  
Altera Corporation  
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