AV-51002
2015.12.16
1-78
FPP Configuration Timing when DCLK-to-DATA[] >1
Symbol
Parameter
Minimum
Maximum
1506(97)
1506(98)
—
Unit
µs
µs
µs
µs
ns
s
tSTATUS
tCF2ST1
nSTATUSlow pulse width
268
—
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time after rising edge on DCLK
DCLKhigh time
(99)
tCF2CK
1506
2
(99)
tST2CK
tDSU
tDH
—
5.5
—
(100)
N – 1/fDCLK
—
tCH
0.45 × 1/fMAX
—
s
tCL
DCLKlow time
0.45 × 1/fMAX
—
s
tCLK
fMAX
tR
DCLKperiod
1/fMAX
—
s
DCLKfrequency (FPP ×8/ ×16)
Input rise time
—
125
40
MHz
ns
ns
µs
—
—
—
tF
Input fall time
—
175
40
tCD2UM
tCD2CU
tCD2UMC
CONF_DONEhigh to user mode(101)
CONF_DONEhigh to CLKUSRenabled
CONF_DONEhigh to user mode with CLKUSRoption on
437
—
4 × maximum DCLKperiod
tCD2CU + (Tinit × CLKUSR
—
period)
Tinit
Number of clock cycles required for device initialization
17,408
—
Cycles
Related Information
FPP Configuration Timing
Provides the FPP configuration timing waveforms.
(97)
This value can be obtained if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
This value can be obtained if you do not delay configuration by externally holding nSTATUSlow.
(98)
(99)
If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
N is the DCLK-to-DATA[]ratio and fDCLK is the DCLKfrequency of the system.
(100)
(101)
The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Arria V GX, GT, SX, and ST Device Datasheet
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