AV-51002
2015.12.16
1-76
FPP Configuration Timing when DCLK-to-DATA[] = 1
Table 1-65: DCLK-to-DATA[] Ratio for Arria V Devices
Configuration Scheme
Encryption
Off
Compression
DCLK-to-DATA[] Ratio (r)
Off
Off
On
On
Off
Off
On
On
1
1
2
2
1
2
4
4
On
FPP (8-bit wide)
FPP (16-bit wide)
Off
On
Off
On
Off
On
FPP Configuration Timing when DCLK-to-DATA[] = 1
When you enable decompression or the design security feature, the DCLK-to-DATA[]ratio varies for FPP ×8 and FPP ×16. For the respective DCLK-
to-DATA[]ratio, refer to the DCLK-to-DATA[]Ratio for Arria V Devices table.
Table 1-66: FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Arria V Devices
Symbol
Parameter
nCONFIGlow to CONF_DONElow
Minimum
Maximum
600
Unit
ns
ns
µs
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
—
—
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
600
2
—
nSTATUSlow pulse width
268
—
1506(93)
1506(94)
—
µs
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
µs
(95)
tCF2CK
1506
µs
(93)
(94)
(95)
You can obtain this value if you do not delay configuration by extending the nCONFIGor the nSTATUSlow pulse width.
You can obtain this value if you do not delay configuration by externally holding the nSTATUSlow.
If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
Arria V GX, GT, SX, and ST Device Datasheet
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