AV-51002
2015.12.16
1-70
NAND Timing Characteristics
Symbol
Description
Min
5
Max
—
Unit
ns
(88)
Tdh
Data to write enable hold time
Tcea
Trea
Trhz
Trr
Chip enable to data access time
Read enable to data access time
Read enable to data high impedance
Ready to read enable low
—
—
—
20
25
ns
16
ns
100
—
ns
ns
Figure 1-17: NAND Command Latch Timing Diagram
NAND_CLE
NAND_CE
Tclesu
Tcesu
Tcleh
Tceh
Twp
NAND_WE
NAND_ALE
Talesu
Taleh
Tdsu
Command
Tdh
NAND_DQ[7:0]
Arria V GX, GT, SX, and ST Device Datasheet
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