AV-51002
2015.12.16
1-66
Ethernet Media Access Controller (EMAC) Timing Characteristics
Symbol
Description
Min
2
Typ
—
Max
—
Unit
ns
Tsu
Th
Setup time for USB_DIR/USB_NXT/USB_DATA[7:0]
Hold time for USB_DIR/USB_NXT/USB_DATA[7:0]
1
—
—
ns
Figure 1-12: USB Timing Diagram
USB_CLK
USB_STP
Td
USB_DATA[7:0]
To PHY
From PHY
Tsu Th
USB_DIR & USB_NXT
Ethernet Media Access Controller (EMAC) Timing Characteristics
Table 1-56: Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Arria V Devices
Symbol
Description
Min
—
Typ
8
Max
—
Unit
ns
Tclk (1000Base-T) TX_CLK clock period
Tclk (100Base-T) TX_CLK clock period
—
40
400
—
—
ns
Tclk (10Base-T)
Tdutycycle
Td
TX_CLK clock period
TX_CLK duty cycle
—
—
ns
45
55
%
TX_CLK to TXD/TX_CTL output data delay
–0.85
—
0.15
ns
Arria V GX, GT, SX, and ST Device Datasheet
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Altera Corporation
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