AV-51002
2015.12.16
1-46
PLL Specifications
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tARESET
Minimum pulse width on the areset
—
10
—
—
ns
signal
FREF ≥ 100 MHz
FREF < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.15
UI (p-p)
ps (p-p)
(65)(66)
tINCCJ
Input clock cycle-to-cycle jitter
750
175
17.5
250(68), 175(69)
25(68), 17.5(69)
175
ps (p-p)
Period jitter for dedicated clock output
in integer PLL
(67)
tOUTPJ_DC
mUI (p-p)
ps (p-p)
Period jitter for dedicated clock output
in fractional PLL
(67)
(67)
tFOUTPJ_DC
mUI (p-p)
ps (p-p)
Cycle-to-cycle jitter for dedicated clock
output in integer PLL
tOUTCCJ_DC
17.5
mUI (p-p)
ps (p-p)
250(68), 175(69)
25(68), 17.5(69)
600
Cycle-to-cycle jitter for dedicated clock
output in fractional PLL
(67)
tFOUTCCJ_DC
mUI (p-p)
ps (p-p)
Period jitter for clock output on a
regular I/O in integer PLL
(67)(70)
tOUTPJ_IO
60
mUI (p-p)
ps (p-p)
600
Period jitter for clock output on a
regular I/O in fractional PLL
(67)(68)(70)
tFOUTPJ_IO
60
mUI (p-p)
(65)
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120
ps.
(66)
(67)
FREF is fIN/N, specification applies when N = 1.
Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the
intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different
measurement method and are available in Memory Output Clock Jitter Specification for Arria V Devices table.
This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz.
This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz.
(68)
(69)
(70)
External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter
Specification for Arria V Devices table.
Arria V GX, GT, SX, and ST Device Datasheet
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