AV-51002
2015.12.16
1-45
PLL Specifications
Max Unit
Symbol
Parameter
Condition
–3 speed grade
–4 speed grade
–5 speed grade
–6 speed grade
–3 speed grade
–4 speed grade
–5 speed grade
–6 speed grade
—
Min
—
—
—
—
—
—
—
—
45
Typ
—
—
—
—
—
—
—
—
50
500(63)
500(63)
500(63)
400(63)
670(63)
670(63)
622(63)
500(63)
55
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
Output frequency for internal global or
regional clock
fOUT
Output frequency for external clock
output
fOUT_EXT
tOUTDUTY
tFCOMP
tDYCONFIGCLK
tLOCK
Duty cycle for external clock output
(when set to 50%)
External feedback clock compensation
time
—
—
—
—
—
—
—
—
—
10
100
1
ns
MHz
ms
Dynamic configuration clock for mgmt_
clkand scanclk
Time required to lock from end-of-
device configuration or deassertion of
areset
tDLOCK
Time required to lock dynamically
(after switchover or reconfiguring any
non-post-scale counters/delays)
—
—
—
1
ms
Low
Medium
High(64)
—
—
—
—
—
0.3
1.5
4
—
—
—
50
MHz
MHz
MHz
ps
fCLBW
PLL closed-loop bandwidth
Accuracy of PLL phase shift
tPLL_PSERR
—
(63)
This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL.
High bandwidth PLL settings are not supported in external feedback mode.
(64)
Arria V GX, GT, SX, and ST Device Datasheet
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