AV-51002
2015.12.16
1-26
Transceiver Specifications for Arria V GX and SX Devices
Transceiver Speed Grade 4
Transceiver Speed Grade 6
Symbol/Description
Condition
Unit
Min
Typ
Max
Min
Typ
Max
Minimum differential eye
opening at the receiver
serial input pins(30)
—
100
—
—
100
—
—
mV
VICM (AC coupled)
VICM (DC coupled)
—
—
670
—
—
—
—
—
4
650(31)/800
—
730
—
—
—
—
10
—
—
—
—
670
—
—
—
—
—
4
650(31)/800
—
730
—
—
—
—
10
—
—
—
mV
mV
Ω
≤ 3.2Gbps(32)
700
85
700
85
85-Ω setting
100-Ω setting
100
120
150
—
100
120
150
—
Ω
Differential on-chip
termination resistors
120-Ω setting
Ω
150-Ω setting
Ω
(33)
tLTR
—
—
—
—
—
µs
(34)
tLTD
—
—
µs
(35)
tLTD_manual
4
—
4
—
µs
(36)
tLTR_LTD_manual
15
—
15
—
µs
Programmable ppm
detector(37)
62.5, 100, 125, 200, 250, 300, 500, and 1000
ppm
(30)
The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable
the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
The AC coupled VICM is 650 mV for PCIe mode only.
(31)
(32)
(33)
(34)
(35)
For standard protocol compliance, use AC coupling.
tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high.
tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high when the CDR is
functioning in the manual mode.
(36)
(37)
t
LTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtorefsignal goes high when the
CDR is functioning in the manual mode.
The rate match FIFO supports only up to 300 parts per million (ppm).
Arria V GX, GT, SX, and ST Device Datasheet
Send Feedback
Altera Corporation
INTEL [ INTEL ]
