AV-51002
2015.12.16
1-25
Transceiver Specifications for Arria V GX and SX Devices
Table 1-21: Transceiver Clocks Specifications for Arria V GX and SX Devices
Transceiver Speed Grade 4
Transceiver Speed Grade 6
Unit
Symbol/Description
Condition
Min
Typ
125
—
Max
Min
Typ
125
—
Max
fixedclkclock frequency
PCIe Receiver Detect
—
—
75
—
—
—
MHz
MHz
Transceiver Reconfigura‐
tion Controller IP (mgmt_
clk_clk) clock frequency
125
75
125
Table 1-22: Receiver Specifications for Arria V GX and SX Devices
Transceiver Speed Grade 4
Min Typ Max
Transceiver Speed Grade 6
Min Typ Max
Symbol/Description
Condition
Unit
Supported I/O standards
Data rate(28)
1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
—
—
611
—
—
—
6553.6
1.2
611
—
—
—
3125
1.2
Mbps
V
Absolute VMAX for a
receiver pin(29)
Absolute VMIN for a
receiver pin
—
—
–0.4
—
—
—
—
–0.4
—
—
—
—
V
V
Maximum peak-to-peak
differential input voltage
VID (diff p-p) before
1.6
1.6
device configuration
Maximum peak-to-peak
differential input voltage
VID (diff p-p) after device
configuration
—
—
—
2.2
—
—
2.2
V
(28)
(29)
To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
The device cannot tolerate prolonged operation at this absolute maximum.
Arria V GX, GT, SX, and ST Device Datasheet
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Altera Corporation
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