AV-51002
2015.12.16
2-64
FPP Configuration Timing when DCLK to DATA[] > 1
Symbol
Parameter
Minimum
Maximum
437
Unit
μs
tCD2UM
CONF_DONEhigh to user mode (213)
CONF_DONEhigh to CLKUSRenabled
175
tCD2CU
4 × maximum DCLK
—
—
period
tCD2UMC
CONF_DONEhigh to user mode with CLKUSRoption on
tCD2CU
+
—
—
(17,408 × CLKUSR
period) (214)
Related Information
•
•
DCLK-to-DATA[] Ratio (r) for FPP Configuration on page 2-57
Configuration, Design Security, and Remote System Upgrades in Arria V Devices
(213)
The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device.
To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the
“Initialization” section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.
(214)
Arria V GZ Device Datasheet
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