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5AGXFA5H4F35C5N 参数 Datasheet PDF下载

5AGXFA5H4F35C5N图片预览
型号: 5AGXFA5H4F35C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 622MHz, 190000-Cell, CMOS, PBGA1152, ROHS COMPLIANT, FBGA-1152]
分类和应用: 时钟可编程逻辑
文件页数/大小: 184 页 / 1761 K
品牌: INTEL [ INTEL ]
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AV-51002  
2017.02.10  
2-78  
Document Revision History  
Term  
Definition  
VOCM  
VOD  
Output common mode voltage—e common mode of the differential signal at the transmitter.  
Output differential voltage sꢂing—e difference in voltage between the positive and complementary conductors of a  
differential transmission at the transmitter.  
VSWING  
VX  
Differential input voltage  
Input differential cross point voltage  
Output differential cross point voltage  
High-speed I/O block—clock boost factor  
VOX  
W
Document Revision History  
Date  
Version  
Changes  
February 2017  
2017.02.10  
• Changed the minimum value for tCD2UMC in the “FPP Timing Parameters for Arria V GZ Devices When the  
DCLK-to-DATA[] Ratio is 1” table.  
• Changed the minimum value for tCD2UMC in the "FPP Timing Parameters for Arria V GZ Devices When the  
DCLK-to-DATA[] Ratio is >1" table.  
• Changed the minimum value for tCD2UMC in the "AS Timing Parameters for AS x1 and AS x4 Configurations  
in Arria V GZ Devices" table.  
• Changed the minimum value for tCD2UMC in the "PS Timing Parameters for Arria V GZ Devices" table.  
• Changed the minimum number of clock cycles value in the "Initialization Clock Source Option and the  
Maximum Frequency for Arria V GZ Devices" table.  
Arria V GZ Device Datasheet  
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Altera Corporation