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5AGXFA5H4F35C5N 参数 Datasheet PDF下载

5AGXFA5H4F35C5N图片预览
型号: 5AGXFA5H4F35C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 622MHz, 190000-Cell, CMOS, PBGA1152, ROHS COMPLIANT, FBGA-1152]
分类和应用: 时钟可编程逻辑
文件页数/大小: 184 页 / 1761 K
品牌: INTEL [ INTEL ]
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AV-51002  
2017.02.10  
2-72  
Programmable IOE Delay  
Programmable IOE Delay  
Table 2-66: IOE Programmable Delay for Arria V GZ Devices  
Available  
Fast Model  
Commercial  
Slow Model  
Parameter (228)  
Min Offset (229)  
Unit  
Settings  
Industrial  
C3  
C4  
I3L  
I4  
D1  
D2  
D3  
D4  
D5  
D6  
64  
32  
8
0
0
0
0
0
0
0.464  
0.493  
0.244  
1.699  
0.492  
0.493  
0.244  
0.924  
0.459  
2.992  
0.924  
0.924  
0.458  
1.011  
0.503  
3.192  
1.011  
1.011  
0.503  
0.921  
0.456  
3.047  
0.920  
0.921  
0.456  
1.006  
0.500  
3.257  
1.006  
1.006  
0.499  
ns  
ns  
ns  
ns  
ns  
ns  
0.230  
1.587  
64  
64  
32  
0.464  
0.464  
0.229  
Programmable Output Buffer Delay  
Table 2-67: Programmable Output Buffer Delay for Arria V GZ Devices  
You can set the programmable output buffer delay in the Quartus II sofꢂare by setting the Output Buffer Delay Control assignment to either  
positive, negative, or both edges, with the specific values stated here (in ps) for the Output Buffer Delay assignment.  
Symbol  
Parameter  
Typical  
0 (default)  
50  
Unit  
ps  
ps  
DOUTBUF  
Rising and/or falling edge delay  
100  
ps  
150  
ps  
(228)  
(229)  
You can set this value in the Quartus II sofꢂare by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column of Assignment Editor.  
Minimum offset does not include the intrinsic delay.  
Arria V GZ Device Datasheet  
Send Feedback  
Altera Corporation