AV-51002
2017.02.10
2-57
JTAG Configuration Specifications
JTAG Configuration Specifications
Table 2-54: JTAG Timing Parameters and Values for Arria V GZ Devices
Symbol
Description
Min
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCP
tJCP
tJCH
tJCL
TCK clock period
30
167 (203)
TCK clock period
—
TCK clock high time
TCK clock low time
14
14
2
—
—
tJPSU (TDI)
tJPSU (TMS)
tJPH
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
JTAG port clock to output
—
3
—
5
—
tJPCO
—
—
—
11 (204)
14 (204)
14 (204)
tJPZX
JTAG port high impedance to valid output
JTAG port valid output to high impedance
tJPXZ
Fast Passive Parallel (FPP) Configuration Timing
DCLK-to-DATA[] Ratio (r) for FPP Configuration
FPP configuration requires a different DCLK-to-DATA[]ratio when you turn on encryption or the compression feature.
(203)
(204)
e minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2V-1.5V when you perform the volatile key programming.
A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO I/O bank = 2.5 V, or 13 ns if it
equals 1.8 V.
Arria V GZ Device Datasheet
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