AV-51002
2017.02.10
2-56
Duty Cycle Distortion (DCD) Specifications
Duty Cycle Distortion (DCD) Specifications
Table 2-52: Worst-Case DCD on Arria V GZ I/O Pins
e DCD numbers do not cover the core clock network.
C3, I3L
C4, I4
Symbol
Unit
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
%
Configuration Specification
POR Specifications
Table 2-53: Fast and Standard POR Delay Specification for Arria V GZ Devices
Select the POR delay based on the MSEL setting as described in the “Configuration Schemes for Arria V Devices” table in the Configuration, Design
Security, and Remote System Upgrades in Arria V Devices chapter.
POR Delay
Minimum (ms)
Maximum (ms)
Fast
Standard
4
12 (202)
100
300
Related Information
Configuration, Design Security, and Remote System Upgrades in Arria V Devices
(202)
e maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize afer the POR trip.
Arria V GZ Device Datasheet
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