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Electrical Characteristics
lists the steady-state voltage and current values expected from Arria V
system-on-a-chip (SoC) devices with ARM
®
-based hard processor system (HPS).
Power supply ramps must all be strictly monotonic, without plateaus.
Table 5. HPS Power Supply Operating Conditions for Arria V SX and ST Devices
Symbol
V
CC_HPS
V
CCPD_HPS
Description
HPS Core voltage and periphery circuitry power supply
HPS I/O pre-driver (3.3 V) power supply
HPS I/O pre-driver (3.0 V) power supply
HPS I/O pre-driver (2.5 V) power supply
HPS I/O buffers (3.3 V) power supply
HPS I/O buffers (3.0 V) power supply
HPS I/O buffers (2.5 V) power supply
V
CCIO_HPS
HPS I/O buffers (1.8 V) power supply
HPS I/O buffers (1.5 V) power supply
HPS I/O buffers (1.35 V) power supply
HPS I/O buffers (1.2 V) power supply
HPS reset and clock input pins (3.3 V) power supply
V
CCRSTCLK_HPS
HPS reset and clock input pins (3.0 V) power supply
HPS reset and clock input pins (2.5 V) power supply
HPS reset and clock input pins (1.8 V) power supply
V
CCPLL_HPS
V
CC_AUX_SHARED
Notes to
(1) Refer to
for the steady-state voltage values expected from the FPGA portion of the Arria V SoC devices.
(2) V
CCPD_HPS
must be 2.5 V when V
CCIO_HPS
is 2.5, 1.8, 1.5, or 1.2 V. V
CCPD_HPS
must be 3.0 V when V
CCIO_HPS
is 3.0 V. V
CCPD_HPS
must be 3.3 V when
V
CCIO_HPS
is 3.3 V.
(3) V
CCIO_HPS
1.35 V is supported for HPS row I/O bank only.
Minimum
1.07
3.135
2.85
2.375
3.135
2.85
2.375
1.71
1.425
1.283
1.14
3.135
2.85
2.375
1.71
2.375
2.375
Typical
1.1
3.3
3.0
2.5
3.3
3.0
2.5
1.8
1.5
1.35
1.2
3.3
3.0
2.5
1.8
2.5
2.5
Maximum
1.13
3.465
3.15
2.625
3.465
3.15
2.625
1.89
1.575
1.418
1.26
3.465
3.15
2.625
1.89
2.625
2.625
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
HPS PLL analog voltage regulator power supply
HPS and FPGA shared auxiliary power supply
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
INTEL [ INTEL CORPORATION ]
