Page 22
Switching Characteristics
Table 21. Transceiver Specifications for Arria V GT and ST Devices (Part 3 of 3)
Transceiver Speed Grade 3
Symbol/
Description
Conditions
Unit
Max
Min
Typ
CMU PLL
Supported data range
—
—
0.611
611
—
—
10.3125
3125
Gbps
Mbps
fPLL supported data range
Transceiver-FPGA Fabric Interface
153.6 (13)
161 (14)
,
Interface speed (PMA direct mode)
—
50
—
MHz
Interface speed
(single-width mode)
—
—
25
25
—
—
187.5
MHz
MHz
Interface speed (double-width mode)
163.84
Notes to Table 21:
(1) The transmitter REFCLKphase jitter is 30 ps p-p (5 ps RMS) with bit error rate (BER) 10-12, equivalent to 14 sigma.
(2) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(3) The maximum peak-to peak differential input voltage of 300 mV is allowed for DC coupled link.
(4) The device cannot tolerate prolonged operation at this absolute maximum.
(5) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you
enable the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(6) The AC coupled VICM is 650 mV for PCIe mode only.
(7) For standard protocol compliance, use AC coupling.
(8) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
(9) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high.
(10) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high when the
CDR is functioning in the manual mode.
(11) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtorefsignal goes high when
the CDR is functioning in the manual mode.
(12) The rate match FIFO supports only up to 300 ppm.
(13) The maximum frequency when core transceiver local routing is selected.
(14) The maximum frequency when core transceiver network routing (GCLK, RCLK, or PCLK) is selected.
(15) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
(16) This specification is only applicable to channels on one side of the device across two transceiver banks.
(17) The Quartus II software allows AC gain setting = 3 for design with data rate between 611 Mbps and 1.25 Gbps only.
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
INTEL [ INTEL ]
